A semiconductor memory device stores data or outputs stored data according to an operation mode. For example, when an external device such as a central processing unit (CPU) requests data, a semiconductor memory device performs a read operation of outputting data corresponding to an address inputted from the external device requesting the data, or performs a write operation of storing data provided from the external device in a position corresponding to the address.
The read and write operations are performed by using an address path. The address path includes a row address path where data stored in a memory cell is sensed and amplified by an sense amplifier after a word line is selected by a row address, and a column address path where one of a plurality of output enable signals Yi<n> is selected by a column address. An operation related to the column address path (hereafter, referred to as ‘column operation’) is controlled by a column path circuit including a column decoder. The column path circuit serves to decode a column address, selectively enable one of the output enable signals Yi<n>, and transmit data loaded on a bit line selected by the enabled output enable signal Yi<n> to an input/output line.
Furthermore, the column operation generates the output enable signals Yi<n> using a strobe clock signal CSTR for strobing an address. A semiconductor memory device includes a plurality of control circuits and a data transmission line for reading or writing data, and an input time point of the strobe clock signal CSTR may vary according to a loading variation, caused by the control circuits and the data transmission line, and a PVT (Process Voltage Temperature) variation during the column operation.
Now, an operation of decoding an address to enable an output enable signal during a known column operation will be described. The operation may be divided into a case FAST in which the input of the strobe clock signal CSTR is early and a case SLOW in which the input of the strobe clock signal CSTR is late, depending on a PVT variation.
FIG. 1 is a timing diagram of output enable signals generated by decoding an address according to a strobe clock signal during the known column operation.
First, when the input time point of the strobe clock signal CSTR is at the case FAST, internal addresses IADD1<1:4> and IADD2<1:8> generated according to a first combination of addresses ADD<1:5> are decoded to enable an output enable signal Yi<n> during a period A where the strobe clock signal CSTR is enabled. However, since the strobe clock signal CSTR is inputted at an earlier time point than a set-up time of the internal addresses IADD1<1:4> and IADD2<1:8>, the output enable signal Yi<n> has a small pulse width. Therefore, an error may occur in the read and write operations of the semiconductor memory device.
Next, when the input time point of the strobe clock signal CSTR is at the case SLOW, the internal addresses IADD1<1:4> and IADD2<1:8> generated according to the first combination of the addresses ADD<1:5> are decoded to enable the output enable signal Yi<n> during a period B where the strobe clock signal CSTR is enabled. However, since the input of the strobe clock signal CSTR is delayed, an input time point of internal addresses IADD1<1:4> and IADD2<1:8> generated according to a second combination of the addresses ADD<1:5> overlaps the enable period of the strobe clock signal CSTR. In this case, since the output enable signal Yi<n> enabled according to the first combination of the addresses ADD<1:5> and an output enable signal Yi<n+1> enabled according to the second combination of the addresses ADD<1:5> are enabled, an error may occur in the read and write operations of the semiconductor memory device.